Job - ASIC Design/Verification Engineer, Hong Kong, Huawei Tech. Investment Co., Ltd.
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Huawei Tech. Investment Co., Ltd.


Huawei is a leading global information and communications technology (ICT) solutions provider. Founded in 1987, Huawei is a private company fully owned by its employees. Our aim is to enrich life and improve efficiency through a better connected world, acting as a responsible corporate citizen, innovative enabler for the information society, and collaborative contributor to the industry. Driven by customer-centric innovation and open partnerships, Huawei has established an end-to-end ICT solutions portfolio that gives customers competitive advantages in telecom and enterprise networks, devices and cloud computing. Huawei’s 170,000 employees worldwide are committed to creating maximum value for telecom operators, enterprises and consumers. Our innovative ICT solutions, products and services are used in more than 170 countries and regions, serving over one-third of the world’s population. 

For more information, please visit Huawei online at www.huawei.com
 

ASIC Design/Verification Engineer, Hong Kong

Job Ref.CT3106479-01#0462

In May 2008, HiSilicon-Huawei setup an R&D center in Hong Kong, focusing on communication chipset development. Today, we are expanding our R&D work to next generation products that would be used in a wide range of Huawei products. We are looking for enthusiastic and high caliber engineers at all levels to join our team, to support the development from system and architectural design, modeling, micro-architecture design to front-end implementations and verification.

The ASIC Design/Verification Engineers will be responsible or take part in implementing or verifying different major functional units of a communication system, focusing on the MAC and physical layer. The individual shall be responsible or contribute to the various phase of the development work, including but not limited to feasibility studies, cost and power estimation, performance and functional modeling, micro-architecture definition, front end design and verification, and synthesis. The individual shall work closely with the rest of the team to deliver the communication SOC that meets the requirements of low cost, low-power, and high performance for wireline networking application.

Responsibilities

  • Perform logic design using synthesis tools for SOC product.
  • Verify design by computer simulation and/ or emulation.
  • Prepare and maintain block diagram, schematics and components information.
  • Oversee and perform layout design, timing analysis and ECO logic changes.
  • Evaluate and characterize FPGA/ASIC prototype units.

Desired Skills and Experience

  • Minimum of 2 years of proven design or verification experience in SOC projects
  • Experience with communication ASIC design/verification is desirable
  • Experience with the design/verification in one or more of the following disciplines
    • DSP Algorithms, e.g. Digital Filters, FFT etc.
    • Forward error correction Algorithm, e.g. LDPC, Reed Solomon, Trellis Coding, Viterbi etc.
    • Noise Cancellation Algorithms/Scheme, e.g. Interleaving, Echo Cancellation, MIMO, etc.
    • Network and High Speed Interfaces, e.g. XGMII, RGMII, GMII, SERDES
    • SOC processor and peripherals, e.g. ARM cores, DSP cores, SPI, UART, GPIO etc.
    • TCP/IP networking/service packet protocols
  • Knowledge of simulation and synthesis tools on FPGA/ASIC
  • Must be a highly organized, detail-oriented self-starter, who works well independently, as well as in a team environment
  • BS or higher degree in Electrical/Computer Engineering.
  • Good verbal and written communication skills 

We offer competitive remuneration package to the right candidate. Interested parties please send you full resume with present and expected salary, available date to andy.kwok@huawei.com; eric.ng@huawei.com .  All information collected is strictly for recruitment purpose.

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Job Ref No.
CT3106479-01#0462
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  • 5-day week
  • 13-month pay
  • Discretionary bonus
  • Medical plan
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