Job ref no.: CT3114389-01#7849

Senior ASIC Design Engineer

ViXS Systems Hong Kong Limited

  • 5-day week
  • Dental plan
  • Flexible working hours
  • Insurance plan
  • Medical plan


  • As a member of the engineering design team, the successful candidate will focus on the development of our next generation IC designs
  • The successful candidate will:
    • take ownership of various VLSI design responsibilities including research, logic design, verification, synthesis and documentation
    • work closely with R&D teams in other sites on design, verification, integration of IPs


  • Masters/Bachelor Degree in Electrical/Computer Engineering or equivalent
  • Proficient oral and written communication skills in English
  • Minimum of 3 years of Verilog or VHDL coding experience
  • Experience with system buses AHB, AXI or OCP
  • Experience with one or more of the following:
    • ARM/ARC processors
    • Video codecs H.264/AVC, HEVC
    • Video processing algorithms such as image scaling, noise reduction, de-interlacing
    • Interfaces PCIe, USB, Ethernet, SD/MMC
  • Experience/knowledge of the following is NOT required, but a plus:
    • Hands on experience with EDA tools (e.g. VCS, NCSIM, Modelsim, dc_shell)
    • UVM methodology



Interested applicants apply by sending the resume, stating the expected salary and start date by clicking Apply Now.  Only shortlisted candidates will be contacted. All information collected will be treated in strict confidence and used only for recruitment purposes.


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More job information
Job ref no. CT3114389-01#7849
  • N/A
Job Function
  • Shatin
Employment Term
  • Permanent
  • Full-time
  • 3 years - 8 years
Career Level
  • Non-management level
  • Degree
  • Master's degree