Senior or Junior Digital IC Design Engineer (Semi-conductor)

Responsibilities

• Participate in digital IP development/evaluation and SOC integration;
• Protocol specification study, signal processing algorithm analysis, design prototyping and IC implementation;
• Working full ASIC design cycle from design, RTL coding, verification, synthesis, timing closure, DFT, backend support and silicon bring-up;

Requirement

• Bachelor or above in Electronic Engineering;
• 5 - 6 years related working experience in semi-conductor industry is preferred, fresh graduates are welcomed;
• Knowledge in ASIC/FPGA design methodology;
• Knowledge in system level design methodology and embedded processors (ARM/MIPS/DSP) MMU/caching, buses (AMBA);
• Knowledge of both front-end, analog and backend flow is an advance;
• Knowledge in OS (Linux) virtual memory/threading/power management is a plus;
• Able to code in 'C' and Verilog RTL;
• Less experienced or fresh graduates are welcomed as "Junior Digital IC Design Engineer";

We offer attractive compensation package (including 5-day work, medical and dental insurance) to the right candidates according to your academic background and working experience. Interested parties please email your full CV with RECENT and EXPECTED salary to HR Department by clicking "Apply Now" below or visit our website www.appotech.com .

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